The present invention relates to a timing signal generating circuit and a variable delay circuit, and more particularly, to a timing signal generating circuit and a variable delay circuit employed in a delay locked loop circuit of a semiconductor memory device.
An LSI device, such as a synchronous DRAM (SDRAM), includes a delay locked loop (DLL) circuit or a phase locked loop (PLL) circuit to generate an internal clock signal. The internal clock signal is generated based on an external clock signal of an external device and used to control the data input timing or data output timing of an internal circuit.
The delay circuit generates the internal clock signal such that it is synchronized with or delayed from an external clock signal in correspondence with changes in the characteristics of the output terminal of the SDRAM. A stub series termination logic (SSTL) interface, which is suitable for high speed processing, is employed as the input/output terminal of the SDRAM. Since the amplitude of the signal generated by the SSTL interface is relatively small, high timing accuracy is required. Jitter of the internal clock signal must be minimized to achieve the timing accuracy. That is, in a DLL circuit, differences in the delay amount of delay elements, which are used to delay the external clock signal, and deviations between a pseudo I/O interface signal generated in the device and an external I/O interface signal must be minimized.
FIG. 1 is a schematic block diagram showing an SDRAM 50. The SDRAM 50 has a memory circuit 51, which includes a data output buffer 52 and a memory circuit block 51a, and a DLL circuit 60. The DLL circuit 60 generates an internal clock signal used to control the output timing of data.
The memory circuit block 51a receives various signals, such as an external clock signal CLK, an external command signal, an address signal, and write data. Based on the external command signal, the memory circuit block 51a performs various processes, such as writing or reading data.
The data output buffer 52 transmits read data RD from the memory circuit block 51a, in accordance with the internal clock signal CK from the DLL circuit 60, to an external input device 54 via an external output terminal 53 of the SDRAM 50 and an SSTL interface 56. The SSTL interface 56 performs level conversion on the theoretical amplitude of the read data RD and generates an external I/O interface signal DQ. The external I/O interface signal DQ is sent to the external input device 54.
FIG. 2 is a circuit diagram showing the data output buffer 52 and the SSTL interface 56. The data output buffer 52 includes a pull-up p-channel (PMOS) transistor Q1 and a pull-down n-channel MOS (NMOS) transistor Q2, which are connected in series between a high potential power supply VDD and a low potential power supply VSS. The read data RD is applied to the gates of the PMOS transistor Q1 and the NMOS transistor Q2 via a transfer gate (not shown), which opens in response to the rising of the internal clock signal CK. The read data RD is output from a node between the PMOS transistor Q1 and the NMOS transistor Q2 and provided to the SSTL interface 56 via the external output terminal 53.
The SSTL interface 56 includes a resistor R1 connected to the external output terminal 53, a pull-up resistor R2 connected to the resistor RI, and a pull-up resistor R3 connected to an external input terminal 55 of the external input device 54. A final voltage VTT is applied to the pull-up resistors R2, R3. A line L is connected to a node between the resistor R1 and the pull-up resistor R2 and a node between the pull-up resistor R3 and the external input terminal 55. The resistor R1 is preferably 25 ohms and the resistors R2, R3 are preferably 50 ohms.
The SSTL interface 56 generates the external I/O interface signal DQ (FIG. 8), which amplitude is smaller than the theoretical amplitude of the read data RD, and sends the external I/O interface signal DQ to the external input terminal 55. An input buffer 54a of the external input device 54 compares the external I/O interface signal DQ to a reference signal VREF and generates a waveform-shaped external I/O interface signal.
As shown in FIG. 1, the DLL circuit 60 includes a clock input buffer 61, a delay circuit section 62, a pseudo interface circuit section 63, a pseudo signal input buffer 64, a determination circuit section 65, and a delay control circuit section 66.
The clock input buffer 61 receives the external clock signal CLK from an external device (not shown) and compares the clock signal CLK with the reference signal VREF to generate a waveform-shaped external clock signal WCLK. The clock input buffer 61 causes the waveform-shaped external clock signal WCLK to go high when the external clock signal CLK becomes equal to or higher than the reference signal VREF and causes the waveform-shaped external clock signal WCLK to go low when the external clock signal CLK becomes lower than the reference signal VREF.
The delay circuit section 62 receives the waveform-shaped external clock signal WCLK and delays it for a predetermined time in accordance with a control signal from the delay control circuit section 66 to generate the internal clock signal CK.
FIG. 6 is a circuit diagram showing the delay circuit section 62, which has a plurality (an n number) of delay circuits DM1-DMn that are connected in series. A high potential power supply VDD and a low potential power supply VSS are applied to each of the delay circuits DM1-DMn via power supply lines Lp, Ln.
The first delay circuit DM1 receives the waveform-shaped external clock signal WCLK from the clock input buffer 61 and sends a delayed clock signal to the next delay circuit DM2 and so on. In this manner, the waveform-shaped external clock signal WCLK is sequentially delayed as it is passed on to the subsequent delay circuits. Thus, the delay between the external clock signal CLK and the delayed clock signal increases at each delay circuit DMn.
The output terminal of each of the delay circuits DM1-DMn is connected to an internal clock signal output line L2 via gate transistors GT1-GTn, which are preferably NMOS transistors. Selection signals SL1-SLn are received from the delay control circuit section 66 to activate a selected one of the gate transistors GT1-GTn. The delayed clock signal output by the delay circuit DMn corresponding to the activated gate transistor is provided to the internal clock signal output line L2. In other words, the delay circuit DMn selected by the delay control circuit section 66 provides the internal clock signal output line L2 with a delayed clock signal that is delayed by a predetermined time. In this manner, a phase controlled internal clock signal CK is generated. The delayed (phase controlled) internal clock signal CK is sent to the data output buffer 52 and the pseudo interface circuit section 63.
The pseudo interface circuit section 63 receives the internal clock signal CK from the delay circuit section 62, converts the level of the internal clock signal CK, and generates a pseudo I/O interface signal dDQ that is an approximation of the external I/O interface signal DQ provided to the external input device 54. In other words, the pseudo interface circuit section 63 has a transmission characteristic that approximates the transmission characteristic of the SSTL interface 56.
FIG. 4 is a circuit diagram showing the conventional pseudo interface circuit section 63, which includes an output portion 63a and an interface portion 63b. The output portion 63a has a pull-up PMOS transistor Q11 and a pull-down NMOS transistor Q12 connected in series between the high potential power supply VDD and the low potential power supply VSS. The internal clock signal CK is provided to the gate of the PMOS transistor Q11 and the gate of the NMOS transistor Q12.
The circuit configuration of the interface portion 63b is equivalent to that of the SSTL interface 56 shown in FIG. 2. An equivalent circuit of the SSTL interface 56 is shown in FIG. 3. This equivalent circuit has a resistor R4, which is preferably 25 ohms, a pull-up resistor R5, which is preferably 25 ohms, and a capacitor C1, which is preferably 30 pF taking into consideration the wire capacitance of the line L.
The interface portion 63b of FIG. 4 has a capacitor C11 and four resistors R11-R14. A voltage divider circuit formed by the resistors R11 and R12 divides the high potential power supply VDD and generates the final voltage VTT. The resistor R13 corresponds to the resistor R4 and receives the internal clock signal CK from the output portion 63a. The resistor R14 corresponds to the pull-up resistor R5 and is provided with the final voltage VTT from the voltage divider circuit. The capacitor C11 corresponds to the wire capacitance of the line L (and the 30 pF capacitor C1) and is connected between the low potential power supply VSS and a node between the resistors R13 and R14.
The pseudo signal input buffer 64 receives the pseudo I/O interface signal dDQ from the pseudo interface circuit section 63, compares the pseudo I/O interface signal dDQ with the reference signal VREF, and generates a waveform-shaped pseudo I/O interface signal WdDQ. The reference signal VREF (determination level) is set at an intermediate level of the theoretical amplitude of the pseudo I/O interface signal dDQ. More specifically, the pseudo signal input buffer 64 causes the waveform-shaped pseudo I/O interface signal WdDQ to go high when the pseudo I/O interface signal dDQ becomes equal to or higher than the reference signal VREF and causes the waveform-shaped pseudo I/O interface signal WdDQ to go low when the pseudo I/O interface signal dDQ becomes lower than the reference signal VREF.
The determination circuit section 65 receives the waveform-shaped pseudo I/O interface signal WdDQ from the pseudo signal input buffer 64 and the waveform-shaped external clock signal WCLK from the clock input buffer 61 to compare the rising of the interface signal WdDQ with the rising of the clock signal WCLK. That is, the determination circuit section 65 compares the phase of the wave-form shaped pseudo I/O interface signal WdDQ with the phase of the clock signal WCLK and provides the comparison result to the delay control circuit section 66.
The delay control circuit section 66 generates the selection signal which activates one of the gate transistors GT1-GTn in the delay circuit section 62 based on the comparison result.
For example, if the waveform-shaped pseudo I/O interface signal WdDQ rises earlier than the clock signal WCLK, the delay control circuit section 66 delays the internal clock signal CK by activating a gate transistor GTn corresponding to the next delay circuit DMn from the currently selected delay circuit. That is, when the phase of the waveform-shaped pseudo I/O interface signal WdDQ is ahead of the waveform-shaped external clock signal WCLK, the delay control circuit section 66 selects the next delay circuit DM in order to delay the phase of the internal clock signal CK.
If the waveform-shaped pseudo I/O interface signal WdDQ rises later than the waveform-shaped external clock signal WCLK, the delay control circuit section 66 advances the internal clock signal CK by activating a gate transistor GT corresponding to a delay circuit DM that is prior to the currently selected delay circuit. That is, when the phase of the waveform-shaped pseudo I/O interface signal WdDQ is delayed from that of the waveform-shaped external clock signal WCLK, the delay control circuit section 66 selects a forward delay circuit DM in order to advance the phase of the internal clock signal CK. In this manner, the internal clock signal CK is generated in cooperation with changes in the characteristics of the output terminal at a timing appropriate for the device 54.
The generation of the final voltage VTT with the voltage divider circuit, which is formed by the resistors R11, R12 in the pseudo interface circuit section 63, increases power consumption. To decrease power consumption, the size of the pseudo interface circuit section 63 may be reduced. However, this results in the pseudo interface circuit section 63 being different from the actual SSTL interface 56 and may consequently increase any deviation between the pseudo I/O interface signal dDQ and the external I/O interface signal DQ.
FIG. 5 is a circuit diagram showing a conventional improved pseudo interface circuit section 71, which has an output portion 71a formed by a PMOS transistor Q3. The source of the PMOS transistor Q3 is connected to the high potential power supply VDD, and the drain of the PMOS transistor Q3 is connected to the pseudo signal input buffer 64. The gate of the PMOS transistor Q3 receives the internal clock signal CK.
The pseudo interface circuit section 71 also has an interface portion 71b, which includes a pull-up resistor R16, a pull-down resistor R17, and a capacitor C12. The pull-up resistor R16 has a first terminal connected to the drain of the PMOS transistor Q3 and a second terminal connected to the high potential power supply VDD. The pull-down resistor R17 and the capacitor C12 each have a first terminal connected to the drain of the PMOS transistor Q3 and a second terminal connected to the low potential power supply VSS.
When the PMOS transistor Q3 is deactivated, the potential Vnl at node nl is set at
Vn1=VDD{R17/(R16+R17)}.
Accordingly, the potential Vn1 at the node n1 may be set as required regardless of manufacturing differences of the PMOS transistor Q3.
In the pseudo interface circuit section 71, the pull-down resistor R17 has a relatively high resistance to suppress the through current flowing from the high potential power supply VDD to the low potential power supply VSS. In other words, the values of the resistors R16, R17 are set so that the current flowing through the pull-down resistor R17 is less than the current flowing through the NMOS transistor Q12 of the pseudo interface circuit section 63. Accordingly, the through current from the high potential power supply VDD to the low potential power supply VSS is controlled and power consumption is reduced.
The rising of the waveform of the pseudo I/O interface signal dDQ (the potential Vn1 at the node n1) in the pseudo interface circuit section 71 is substantially the same as the rising of the waveform of the pseudo I/O interface signal dDQ in the pseudo interface circuit section 63.
However, the resistance of the pull-down resistor R17 in the pseudo interface circuit section 71 is relatively greater. Thus, the falling of the waveform of the pseudo I/O interface signal dDQ is more gradual. As a result, an increase in the frequency of the external clock signal CLK makes accurate reproduction by the pseudo signal input buffer 64 difficult. That is, with reference to FIG. 9, due to the gradual falling waveform of the pseudo I/O interface signal dDQ, when the internal clock signal CK rises in accordance with the rising of the next external clock signal CLK, the pseudo I/O interface signal dDQ rises before completely falling to the theoretical amplitude low level. Therefore, with reference to FIG. 10, the time period tPD2 between the level of the pseudo I/O interface signal dDQ and the determination level of the pseudo signal input buffer 64 (reference signal VREF) is shorter than the time period tPD1 between the theoretical low level and the determination level. This decreases the accuracy of the internal clock signal CK and may thus cause jitter.
It is a first object of the present invention to provide a timing signal generating circuit for generating a highly accurate timing signal.
It is a second object of the present invention to provide a variable delay circuit that controls the phase of the clock signal with high accuracy.
To achieve the above objects, the present invention provides a circuit for generating a timing signal having a first voltage level and a second voltage level. The circuit includes an active circuit for setting the first voltage level of the timing signal in response to a clock signal, a passive circuit for setting the second voltage level of the timing signal, and a signal transition accelerating circuit connected to the active and passive circuits to accelerate transition of the timing signal from the first voltage level to the second voltage level.
Another aspect of the present invention provides a delay locked loop (DLL) circuit for comparing a phase of a timing signal with a phase of an external clock signal, controlling the phase of the external clock signal in accordance with the comparison result, and generating an internal clock signal having a first voltage level and a second voltage level. The DLL circuit includes a timing signal generating circuit for generating a timing signal having a third voltage level and a fourth voltage level from the internal clock signal. The third and fourth voltage levels differ from the first and second voltage levels. The timing signal generating circuit includes an active circuit for setting the third voltage level of the timing signal when the internal clock signal transitions from the first voltage level to the second voltage level, a passive circuit for setting the fourth voltage level of the timing signal when the internal clock signal transitions from the second voltage level to the first voltage level, and a signal transition accelerating circuit connected to the active and passive circuits to accelerate the transition of the timing signal from the third voltage level to the fourth voltage level.
A further aspect of the present invention provides a semiconductor memory device including a delay locked loop (DLL) circuit for generating an internal clock signal having a first voltage level and a second voltage level from an external clock signal. The DLL circuit includes a determination circuit for comparing a phase of a timing signal with a phase of the external clock signal to generate a comparison signal, a delay circuit for delaying the external clock signal in accordance with the comparison signal to generate the internal clock signal, and a timing signal generating circuit connected to the delay circuit to generate the timing signal having a third voltage level and a fourth voltage level from the internal clock signal. The third and fourth voltage levels differ from the first and second voltage levels. The timing signal generating circuit includes an active circuit for setting the third voltage level of the timing signal when the internal clock signal transitions from the first voltage level to the second voltage level, a passive circuit for setting the fourth voltage level of the timing signal when the internal clock signal transitions from the second voltage level to the first voltage level, and a signal transition accelerating circuit connected to the active and passive circuits to accelerate the transition of the timing signal from the third voltage level to the fourth voltage level.
A further aspect of the present invention provides a variable delay circuit including a plurality of delay elements connected between a pair of power supply lines, and a filter element connected to each of the delay elements.
A further aspect of the present invention provides a variable delay circuit including a plurality of delay elements connected between a pair of power supply lines, and a power consumption circuit connected between the pair of power supply lines to consume power when each of the delay elements are inactive.
A further aspect of the present invention provides a variable delay circuit including a plurality of delay elements connected between a pair of power supply lines, a filter element connected to each of the delay elements, and a power consumption circuit connected between the pair of power supply lines to consume power when each of the delay elements are inactive.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.